Information for BareMetalArcSingle

This page provides detailed information about the BareMetalArcSingle Virtual Platform / Virtual Prototype.

Bare Metal Platform for an ARC Processor. The bare metal platform instantiates a single ARC processor instance. The processor operates using little endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The platform can be passed any application compiled to an ARC elf format. ./platform..exe --program application..elf

Open Source Apache 2.0

BareMetal platform for execution of ARC binary files compiled with FOSS for Synopsys DesignWare ARC Processors CrossCompiler toolchain.

None, baremetal platform definition

The BareMetalArcSingle virtual platform is located in an Imperas/OVP installation at the VLNV: / platform / BareMetalArcSingle / 1.0.

Platform Summary

Table 1: Components in platform

Busbus(builtin)address width:32

Platform Simulation Attributes

Table 2: Platform Simulation Attributes

stoponctrlcstoponctrlcStop on control-C

Command Line Control of the Platform

Built-in Arguments

Table 3: Platform Built-in Arguments

allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.

Processor [] instance: cpu1

Processor model type: 'arc' variant '700' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/
- the OVP website: OVP_Model_Specific_Information_arc_700.pdf

ARC 700 processor model (ARCv1 architecture)

Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately.
Instruction and data caches are not modeled, except for the auxiliary register interface.
External host debug is not modeled, except for the auxiliary register interface.
Real-world timing effects are not modeled. All instructions are assumed to complete in a single cycle.

Models have been validated correct in a cooperative project between Imperas and ARC

ARC Processor ARC6xx/ARC7xx Reference Documentation

The model has been designed for debug using GNU gdb ARCompact/ARCv2 ISA elf32 version 7.5.1. To ensure correct behavior, enter the following command into gdb before attempting to connect to the processor:
set architecture ARC700
Failure to do this may cause the debugging session to fail because of g-packet size mismatch.

The model implements the full ARCv1 instruction set.
The exact set of core instructions present can be configured by a number of parameters: see information for opt-swap, opt-bitscan, opt-extended-arith and opt-multiply in the table below.
Timer 0 and Timer 1 can be enabled using parameters opt-timer0 and opt-timer1, respectively.
The versions of DCCM and ICCM build config registers can be specified using parameters opt-dccm-version and opt-iccm-version, respectively. The sizes of DCCM, ICCM0 and ICCM1 can be specified using parameters opt-dccm-size, opt-iccm0-size and opt-iccm1-size, respectively. Reset base addresses for the ICCMs can be specified using opt-iccm0-base and opt-iccm1-base. Note that the DCCM reset base address is architecturally defined (0x80000000) and not configurable. When CCMs are present, bus ports called DCCM0, ICCM0 and ICCM1 are created so that CCM contents may be viewed or modified externally by connecting to these ports. Parameter opt-internal-ccms specifies whether CCM memory is modeled internally or externally. If modeled externally, the CCMs must be implemented on a bus which is then connected to the CCM bus ports listed above (this parameter is ignored if CCM ports are unconnected; in that case, CCMs are always modeled internally). Parameter opt-reset-internal-ccms indicates that internally-modeled CCMs should be cleared to zero on a processor reset; if False, then internally-modeled CCMs retain their previous state after a reset.
The set of core registers can be specified using parameter opt-extension-core-regs. This is a 64-bit value in which a 1-bit implies the presence of that core extension register. For example, a value of 0xf00000000ULL implies that extension registers r32-r35 should be configured.
The reset value of the exception vector base register can be specified using parameter opt-intvbase-preset.

Auxiliary Register External Implementation
If parameter "enable-aux-bus" is True, an artifact 36-bit bus "Auxiliary" is enabled. Slave callbacks installed on this bus can be used to implement auxiliary register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). An auxiliary with 32-bit index 0xABCDEFGH is mapped on the bus at address 0xABCDEFGH0.

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu1' Parameters (Configurations)

mips100The nominal MIPS for the processor
semihostvendorarc.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostnamearcNewlibThe VLNV name of a Semihost library

Table 5: Processor Instance 'cpu1' Parameters (Attributes)

Parameter NameValueType

Memory Map for processor 'cpu1' bus: 'bus'
Processor instance 'cpu1' is connected to bus 'bus' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus' using master port 'DATA'.

Table 6: Memory Map ( 'cpu1' / 'bus' [width: 32] )

Lo AddressHi AddressInstanceComponent

Net Connections to processor: 'cpu1'
There are no nets connected to this processor.

Other Sites/Pages with similar information

Information on the BareMetalArcSingle Virtual Platform can also be found on other web sites : has the library pages has more information on the model library

A couple of documents (from other related sites that might be of interest) Control File User Guide VMI Run Time (VMI RT) API Reference Guide

Two Videos on these models (from other sites) ARM Bare Metal Demos Video Presentation MIPS Demo Video Presentation

Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS